Since the release of the Ryzen 7 parts, AMD had promised future updates for its brand new architecture. As of now, AMD is keeping their word with their new AGESA update.
In AMD’s latest update they have released a lot of information on their new AGESA 126.96.36.199 “AMD Generic Encapsulated System Architecture” update, which is designed to add additional overclocking support to AMD Ryzen motherboards and offer support for a wider range of memory DIMMs.This new update also enables IOMMU groups, which will be very useful for those that want to create virtual machines with dedicated graphics.
One of the most noteworthy additions for AMD’s new AGESA 188.8.131.52 update is support for higher clocked memory, moving beyond 3200MHz and allowing motherboards to support memory that is up to 4000MHz in speed without the need to use BCLK overclocking.
In addition to this AMD has added 26 new parameters for memory adjustment, which are all detailed below. These new values will help some people gain extra performance in their systems via overclocking or stabilise their systems when using faster memory.
Below is a table where AMD has provided in-depth details on every new setting available and how it may help system stability or performance.
|Memory clocks||Added dividers for memory clocks up to DDR4-4000 without ref CLK adjustment. Please note, that values greater than DDR4-2667 are overclocking. Your mileage may vary (as noted by our big overclocking warning at the end of this blog).||133.33MT/s intervals (2667, 2933, 3067, 3200, 3333, 3466, 3600, 3733, 3866, 4000)|
|Command rate (CR)||The amount of time, in cycles, between when a DRAM chip is selected and a command is executed. 2T CR can be very beneficial for stability with high memory clocks, or for 4-DIMM configurations.||2T, 1T|
|ProcODT (CPU on-die termination)||A resistance value, in ohms, that determines how a completed memory signal is terminated. Higher values can help stabilise higher data rates. Values in the range of 60-96 can prove helpful.||Integer values (ohms)|
|tWCL/tWL/tCWL||CAS Write Latency, or the amount of time it takes to write to the open memory bank. WCL is generally configured equal to CAS or CAS-1. This can be a significant timing for stability, and lower values often prove better.||Integer values (cycles)|
|tRC||Row cycle time, or the number of clock cycles required for a memory row to complete a full operational cycle. Lower values can notably improve performance, but should not be set lower than tRP+tRAS for stability reasons.||Integer values (cycles)|
|tFAW||Four activation window, or the time that must elapse before new memory banks can be activated after four ACTIVATE commands have been issued. Configured to a minimum 4x tRRD_S, but values >8x tRRD_S are often used for stability.||Integer values (ns)|
|tWR||Write recovery time or the time that must elapse between a valid write operation and the pre-charging of another bank. Higher values are often beneficial for stability, and values < 8 can quickly corrupt data stored in RAM.||Integer values (ns)|
|CLDO_VDDP||Voltage for the DDR4 PHY on the SoC. Somewhat counterintuitively, lowering VDDP can often be more beneficial for stability than raising CLDO_VDDP. Advanced overclockers should also know that altering CLDO_VDDP can move or resolve memory holes. Small changes to VDDP can have a big effect, and VDDP should not be set to a value greater than VDIMM-0.1V. A cold reboot is required if you alter this voltage.
Sidenote: pre-184.108.40.206 BIOSes may also have an entry labelled “VDDP” that alters the external voltage level sent to the CPU VDDP pins. This is not the same parameter as CLDO_VDDP in AGESA 220.127.116.11.
|Integer values (V)|
|tRDWR / tWRRD||Read-to-write and write-to-read latency, or the time that must elapse between issuing sequential read/write or write/read commands.||Integer values (cycles)|
|tRDRD / tWRWR||Read-to-read and write-to-write latency, or the time between sequential read or write requests (e.g. DIMM-to-DIMM, or across ranks). Lower values can significantly improve DRAM throughput, but high memory clocks often demand relaxed timings.||Integer values (cycles)|
|Gear down Mode||Allows the DRAM device to run off its internally-generated ½ rate clock for latching on the command or address buses. ON is the default for speeds greater than DDR4-2667, however, the benefit of ON vs. OFF will vary from memory kit to memory kit. Enabling Gear down Mode will override your current command rate.||On/Off|
|Rtt||Controls the performance of DRAM internal termination resistors during nominal, write, and park states.||Nom(inal), WR(ite), and Park integers (ohms)|
|tMAW||Maximum activation window, or the maximum number of times a DRAM row can be activated before adjacent memory rows must be refreshed to preserve data.||Integer values (cycles)|
|tMAC||Maximum activate count or the number of times a row is activated by the system before adjacent row refresh. Must be equal to or less than tMAW.||Integer values (cycles)|
|tRFC||Refresh cycle time, or the time it takes for the memory to read and re-write information to the same DRAM cell for the purposes of preserving information. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRFC2||Refresh cycle time for double frequency (2x) mode. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRFC4||Refresh cycle time for quad frequency (4x) mode. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRRD_S||Activate to activate delay (short), or the number of clock cycles between activate commands in a different bank group.||Integer values (cycles)|
|tRRD_L||Activate to activate delay (long), or the number of clock cycles between activate commands in the same bank group.||Integer values (cycles)|
|tWR||Write Recovery time or the time that must elapse between a valid write operation and the pre-charging of another bank. Higher values are often better for stability.||Integer values (ns)|
|tWTR_S||Write to read delay (short), or the time between a write transaction and read command on a different bank group.||Integer values (cycles)|
|tWTR_L||Write to read delay (long), or the time between a write transaction and read command on the same bank group.||Integer values (cycles)|
|tRTP||Read to precharge time, or the number of clock cycles between a READ command to a row and a precharge command to the same rank.||Integer values (cycles)|
|DRAM Power Down||Can modestly save system power, at the expense of higher DRAM latency, by putting DRAM into a quiescent state after a period of inactivity.||On/Off|
AGESA 18.104.22.168 is now available to motherboard manufacturers and is already available to consumers who use the ASUS Crosshair VI Hero and the companies latest beta BIOS. This update is expected to be available widely from mid-late June, depending on how long it takes each motherboard manufacturer to develop and Q/C new BIOS files.